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设计验证工程师design and functional verification engineer (dfv) 面议
西安雁塔区 3年以上 本科
  • 带薪年假定期体检弹性工作
西安紫光国芯半导体有限公司 2024-05-22 15:58:43 2349人关注
职位描述
职位描述:
responsibilities:
1.according to the design specification, be responsible for the verification plan and verification objective definition.
2.test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, vrad) and integration.
3.work with random verification methodology(vmm, ovm, uvm, erm)
4.work as an independent verification engineers to check the design functionality at soc module level and chip level.
5.work as interface with front-end and back-end engineer to optimize or review the design architecture and implementation.
6.verilog or vhdl coding according to design specification or external/internal ip integration.
7.support the post simulation with gate-level verilog or vhdl netlist.
requirements:
1.either bachelor, master or phd in microelectronics, electronic engineering, or related field, 2+ years of verification working experience.
2.experience with verification language (specman/e-language, system-verilog, vera)
3.experience with rtl coding and simulators (modelsim, nc-sim).
4.basic knowledge of script language (perl, tcl, c-language and so on)
5.knowledge about 2g/3g/lte handset baseband architecture, arm, ahb architecture is a plus.
6.knowledge about baseband chip peripheral(usb2.0/usb3.0, ssic, mipi) is a plus.
7.team oriented, love to work in young, international and highly motivated teams.
8.good command of english
联系方式
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工作地点
地址:西安雁塔区西安-科技二路
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