岗位职责:1.负责开发在不同制程及工具软件上的数字逻辑单元的时序功耗模型。2.负责在较短的时间内，在先进的制程中提供标准逻辑的开发流程和设计方法，以满足高质量、高精度的要求。1. Library/IP circuits design, pre/post simulation, characterization for Standard Cell, Standard I/O, SRAM, ROM, Emb-Flash, EEPROM, and other special mixed-signal/analog IP etc. 2. Work closely with layout engineer. Provide the guideline and help for physical layout floor plan, design, verification and RC extraction. 3. Wafer or package chip testing and debug. 4. Customer support. 任职资格:1.微电子、计算机科学、电子科学与技术等相关领域知识的硕士含以上人员。2.熟悉PPA的优化数字逻辑电路和晶体管级电路设计知识3.具有数字逻辑电路分析与表征的经验4.熟悉经验验证/ FineSim模拟包括一些统计分析工具熟悉Verilog、Synthesis 和STA知识熟悉脚本语言，如Perl或者Python /壳/ TCL等1. Good knowledge of circuits design. Experience in Std. Cell, I/O, ESD SRAM, memory compiler, non-volatile memory, charge pump, band gap and other mixed-signal/analog IP preferred. 2. Experience in Cadence/Synopsys/Mentor/Springsoft circuit and layout design/simulation/verification tools preferred. 3. Unix/Lunix system experience and Good programming skills preferred, such as C, Perl, TCL etc. 4. Device/Process/Layout/Testing related experience preferred. 5. Intelligent and excellent analysis capability. 6. Self-motivated and hard work. 职能类别：集成电路IC设计/应用工程师半导体技术 关键字：半导体ICStd.CellI/OTSMC台积电