岗位职责:Job Description: ：1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.2. Design flow/methodology development and innovation for front-end design challenges.3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips. 任职资格:职位要求：1. MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.2. 3 years working experience.3. Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.4. Familiar with tcl/Perl/Python program. 职位要求：1. 电子、计算机等相关专业，硕士及以上学历的应届毕业生。2. 具备基本RTL读写与仿真能力。3. 熟悉使用一种或多种IC前端工具（综合、可测性设计、存储器内建自测试、形式验证、静态时序分析）者优先。4. 具备数字集成电路设计背景和熟悉静态时序分析者优先。5. 熟悉TCL/Perl/Python一种或多种者语言者优先。 职能类别：数字前端工程师